What’s Going On With c1c2s in nodes?

In your debug logs, nodes appears as an array of objects where one of the properties is c1c2s, and it's currently an empty array (Array(0)). While I couldn’t load the exact file content, based on naming conventions in these transistor-level simulation projects, c1c2s almost certainly refers to the two "clock phases" or control lines used in CMOS transistor circuits—commonly known as C1 and C2.

Context in Visual-ULA / Visual-ARM Systems:

The original Visual 6502 project reconstructs transistor-level behavior from silicon imagery to simulate how the 6502 chip functions visualizing every transistor, gate, and clock phase controlling them 
visual6502.org
visual6502.org
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The Visual ARM1 simulation (ARM1 Gate-level Simulation) follows a similar approach applied to the ARM1 architecture—mapping out transistor definitions (transdefs.js), wiring them into gates and nodes, and simulating their behavior under toggling clock phases and input signals 
retrocomputingforum.com
visual6502.org
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In CMOS design, gates often require two-phase non-overlapping clock signals labeled "C1" and "C2" (often used in dynamic logic or transmission-gate circuits). These dictate the timing for when inputs are latched or when precharge and evaluation occur.

So, in transdefs.js, each transistor definition (transdefs[i]) likely includes its role in the clocking phases (C1, C2), sourcing that data into the property's c1c2s array for each node. When you see c1c2s: Array(0) in nodes, it simply means that for those particular nodes (groupings of transistors forming logic gates or nets), no clock-phase information was assigned—they’re probably static logic paths not gated by C1 or C2.